[Research Grant] Ferroelectrics for Nanoelectronics (FERN)
Ente: Engineering and Physical Sciences Research Council
Scadenza: 2013-11-30
Importo max: 528.498 EUR
Paese: GB
Descrizione
The evolution of silicon technology since the 1960's has focussed on doubling performance and functionality every 18-24 months through miniaturization. Critical dimensions measured in tens of nanometres are now common place and billions of components connected by miles of wiring can be packed onto a wafer no larger than a thumb nail. Today the focus is shifting away from more scaling (called more Moore after the founder of Intel, Gordon Moore) towards increasing functionality through the introduction of mixed technologies on silicon (called more than Moore). This project investigates the incorporation of ultra thin ferroelectric materials into silicon nanoelectronics and two of its many applications.Capacitance is the rate of change of charge with voltage. It is the defining property of capacitors which are necessary in many electronic systems but are relatively large. Ferroelectrics can shrink capacitors by three orders of magnitude, because their electric permittivity is so high. More than that, their capacitance can be made to vary depending on the applied voltage so very small and tunable capacitors can be made, which can find applications in hand held electronics products in order to reduce power consumption. If they could be integrated onto a silicon microchip there would be further space savings. Thin layers are expected to produce even higher capacitance. However there is evidence that capacitance starts to reduce below 50 nm as dead layers are said to form near the interface with electrodes, but this may be an interface effect which can be lessened through engineering. Recently there has been experimental evidence that effective negative capacitance can be seen in ultra-thin ferroelectric films. If such material can be incorporated into a transistor then it would be able to reduce the voltage needed to switch a transistor between its on and off states (the sub-threshold slope). This would transform silicon technology, allowing a new generation of more powerful single core processors. Modern computers have dual or multi-core processors. A single core processor would generate too much heat but is still desirable for many applications. Capacitance places a lower limit on the sub-threshold slope. The consequence is that transistors need a larger applied voltage to be on and/or will leak current and so can never be fully switch off. This leads to increased power loss and heating as more transistors are crammed onto the same area of silicon, which limits component density. Integrating a ferroelectric film with negative capacitance into the gate of a transistor would reduce the overall capacitance and thus the sub-threshold swing. The need to understand and produce high quality ferroelectric ultra-thin films is imperative for each of these applications. Atomic Layer Deposition (ALD) at Newcastle and Pulsed Laser Deposition (PLD) at Imperial College will be used to deposit thin films of the ferroelectric materials barium titanate (BTO) and bariu
Settori: Electrical, Electronic & Computer Eng
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